A 32 nm CNFET Model Voltage Controlled Oscillator based ADC Design for Computation-in-Memory Architecture using Emerging ReRAM’s

Abstract

Abstract: Applications that are becoming more and more computationally demanding are beyond the capabilities of traditional Von Neumann systems. By adopting new architectural technologies, these flaws can be rectified. Specifically, Resistive Random Access Memory (ReRAM)-based Computation-In-Memory (CiM) holds great promise for satisfying the computational demands of data-intensive applications like database searches and neural networks. In CiM, calculation is carried out analogously; the potential of CiM is hampered by the expensive, time-consuming, space and energy intensive digitalization of the results. To enhance the functionality and energy efficiency of the CiM architecture, an effective Voltage-Controlled Oscillator (VCO)–based analog-to-digital converter (ADC) designed. The proposed ADC can be used per-column rather than sharing one ADC across several columns because of its efficiency. This will increase the CiM crossbar array's overall efficiency and parallel execution. A Multiplication and Accumulation (MAC) technique used in ReRAM-based CiM crossbar arrays is used to evaluate the proposed ADC. The ADC architecture is designed in Cadence Virtuoso, CMOS 45nm technology and then the complete design is implemented using CNFET 32nm Technology, considering its advantages. Figure of Merit, Resolution, delay, signal to noise ratio and power consumption of VCO-ADC are analyzed and compared with other ADCs.

Index Terms: VCO Based ADC, ReRAM, CNFET Technology.