Low Power MIPS-RISC Processor: A Survey

Abstract

This paper describes how low power strategies were used in the design and implementation of low power RISC processors. With the growing demand for energy- efficient computing devices, reduced power usage is now a crucial design factor. The paper provides a detailed analysis of the many low power strategies that can be implemented to lower RISC Processors power consumption. Clock gating, power gating, dynamic voltage and frequency scaling, and instruction set architectural optimizations are a few of these methods. The paper also discusses the impact of these techniques on CPU performance. These techniques introduce the design and implementation of a low-power RISC processor. The results of the experiments demonstrate that the suggested strategies are capable of reducing power usage by up to 50% without adversely compromising processor performance. This paper demonstrates the feasibility of designing low power RISC processors using low power techniques, making them suitable for use in portable and battery-operated devices.

Index Terms: MIPS, RISC, Low Power, Clock Gating, Xilinx.