A Weighted Pseudorandom Test Pattern Generator for a Built In Self Test Architecture

Abstract

Abstract: As the submicron technology emerges, there arises a huge requirement for increase in the functionality that the chip can perform. In the present generation, massive production of IC requires a rigorous testing to differentiate the perfect chip from the fault one. Verification Engineers has to be aware of the functionality of the chip for a full-scale verification to identify the product failures. Conventional testing requires huge amount of time and circuit complexity and hence these techniques are not suitable for the present generation. Hence there arises a need for the automatic test pattern generation with high randomness between the test pattern generations. Galois Fields are used to generate the randomness in the test pattern generation. In addition to that weighted test pattern generator has been used in the present work to increase the randomness in the test pattern generation. The algorithm was verified using Verilog and realized in VIVADO. The present work has been aimed at optimizing area and delay of the design and it has produced promising results.

Index Terms: Built In Self-Test, circuit under test, test pattern generator, Pseudorandom TPG.