A High-Performance FIR Filter Architecture using Symmetry and Distributed Arithmetic Logic

Abstract

Abstract: In this paper, the symmetry type Finite Impulse Response (FIR) filters are described using distributed arithmetic (DA) logic. The direct-form type filter architecture is considered for the implementation. Direct-form is requires a fewer number of registers than transposed form architecture. The symmetry in the filter coefficients decreases the number of multipliers. Due to the reduction of multipliers, the area and power parameters are reduced by 50%, because multipliers complex block in terms of area and power. Further, the multipliers are completely replaced with shift and add operations to reduce the complexity using DA. In this work, the higher-order filters are decomposed into smaller filter blocks to reduce the Look-up-table (LUT) complexity. The proposed DA-based symmetry FIR filter is validated using FPGA and synthesized using Genus tools from Cadence in 90nm CMOS technology. The physical design is done using Innovus tools from Cadence and the layout of the proposed architecture is generated. The utilization of hardware blocks, delay, area, and power consumption parameters are compared with existing FIR filter architectures.