Speculative Carry Addition Performance Improvement and Area Optimization using Modified Carry Generators

Abstract

Abstract: Carry Speculative Adder (CSPA) is a technique for reducing the critical path delay of an arithmetic circuit that is designed using the carry speculation technique, with an assumption that the carry-out bit generated at a given position of input bits is only a dependent on the previous 'x' bits but not the LSB bit. Carry predictor, internal carry generator, sum generator blocks, and multiplier blocks are used in this architecture. The n-bit CSPA is subdivided into smaller block adders, each of which runs in parallel. A carry predictor circuit serves as a selection line for the multiplexer, with its inputs coupled to the bit pattern generated by internal carry generators, one of which is connected to binary one (vdd) and the other to binary zero (gnd). Each block adder is y bits in size, and the CSPA has 'm' independent block adders and '(m-1)' carry predictor circuits, where p = (n/y). With Carry Speculative Addition, modified carry generators are employed to minimize critical path delays and the consequent need for area and power. Data latching circuits are adjusted to provide continuous data to the circuit. In order to obtain accurate results, the CSPA with Modified Carry Generators (CSPA-M) is built using error detection and error recovery circuitry (VLCSPA-M). The proposed Carry Speculative Addition with Modified Carry Generator architecture is developed using Verilog HDL in both FPGA and ASIC platforms, and the design is simulated using Xilinx ISE and Cadence 45 nm Technology libraries.

Index Terms: Carry Speculative Adder (CSPA), Modified Carry Generator (CSPA-M), Verilog - HDL, FPGA – Xilinx ISE, ASIC – Cadence.