Implementation of Optimized FIR Filter using Reversible Logic

Abstract

Abstract: The Finite Impulse Response (FIR) filter is extensively used in mobile and wireless applications.  Low power and low complexity FIR filters architectures are essential to implement these applications. For signal processing applications, FIR Filter is the most frequently used hardware block. The performance enhancement in the FIR filter is a great challenge. In this paper, two different but effectual methods have been implemented in Xilinx software to improve the performance metrics in terms of speed, area and power.

The first FIR filter is implemented using a normal architecture. The second type of FIR filter is based on Pipelined Technique.  In this technique, throughput is enhanced by utilizing the retiming effectively. Due to this performance also increases gradually. Implementing the FIR Filter using Reversible Vedic Multiplier with both adders i.e. Reversible Carry Look Ahead Adder and Reversible Carry Select Adder can optimize the performance in terms of Power, Delay and utilization. The proposed architecture is implemented using IP Integrator in Xilinx Vivado by utilizing the ZYNQ Zed Board which can be used for DSP Applications.