FPGA Implementation of CORDIC – I using Redundant Arithmetic

Abstract

Abstract: This paper provides high speed, low power consumption, and less area utilization of the Coordinate Rotation Digital Computer (CORDIC) Algorithm for digital signal processing applications. Here methodology is built on a multiplexer-based, that is used to accomplish the fast and efficient hardware on FPGA for sine and cosine values. A 6-stage CORDIC is calculated by four arrangements scheduled i.e., Unrolled CORDIC and MUXes based CORDIC with and without pipelining up to three stages. The proposed architecture has adders, subtractors, and shifters. Shifters are replaced with multiplexers up to 3-stages. All remaining adders and subtractors are traded with Redundant Arithmetic. A 16-bit CORDIC algorithm is designed to achieve the sine and cosine function values by using VIVADO 20.1. Comparisons are performed between Unrolled CORDIC structure and MUXes based CORDIC structure for sine and cosine values in terms of timing and power consumed. MUXes based CORDIC structure attains high operating frequency, less area utilization, and low power consumption for hardware implementation.