Low Power PCI Controller using Design Compiler

Abstract

Abstract: As the technology is shrinking, industries are
facing many challenging issues due to the design complexities
involved in it. The three main factors that drive the digital
design industries are speed, power and area. This paper
explains the different steps to generate a technology specific
gate level net list from the Hardware Description Languages
(HDL), using the Design Compiler Synthesis tool of Peripheral
Component Interconnect (PCI) Controller along with the use
of four masters i.e., Video Data set, Video Codec, IEEE 1394
bus and Personal Computer (PC). It also explains about the
different low power checks along with power and area reports
when the design operates at different Process-VoltageTemperature (PVT) corner. Apart from above the above
details, it also describes Low- Vt (LVT), High-Vt (HVT) cells
and their impact on power consumption in a design along with
the special management cells like isolation and level shifter
cells etc.

Index Terms: Peripheral Component Interconnect (PCI)
Arbiter, Register Transfer Logic (RTL), Unified Power Format
(UPF), Application Specific Integrated Circuits (ASIC), Design
Compiler (DC), Synopsys Low Power Signoff Verification (VC
LP).