VLSI Implementation of Seed Transistor for Super Gate Design based on Grid based Transistor Network Generation

Abstract

In VLSI digital design, the Propagation Delay, Power Dissipation and Area of circuits are strongly related to the number of transistors which are present on an IC. Hence transistor optimization is special interest when designing digital integrated circuits. Therefore, efficient algorithms are used to generate optimized transistor networks, which are quite useful for designing digital integrated circuits (ICs). Several methods have been proposed for generating and optimizing transistor networks. Most Traditional solutions are based on factoring Boolean expressions in which only Chain - Parallel (CP) arrangement of transistors can be obtained from factored forms. Whereas grid-based methods are able to find CP and also non - CP (NCP) arrangements with potential reduction of transistor count. This method is an effective way of improvising VLSI circuits. In this an efficient algorithm is proposed i.e. Novel (Seed) method. It is automatically generates networks with minimal transistor count starting with irredundant sum of products (ISOPs) as inputs. Novel method is able to deliver both CP switching networks and NCP switching network arrangements, which improves VLSI circuit’s performance in terms of area, power and delay. All the network circuits are implemented in ASIC Cadence by using 45nm and 90nm technology with GPDK libraries. By using Cadence Virtuoso tool, it can obtain schematics of design and its test bench, power analysis, SPICE simulation and its simulation waveform.