Design and Implementation of Low Power Finite Impulse Response Filters

Abstract

The Finite Impulse Response (FIR) filter is widely used in mobile and wireless applications. For these applications, the low power and low complexity FIR filter architectures are required. The FIR filter is most commonly used hardware block for signal processing in the above applications. The performance improvement of FIR filter is a great challenge. The researchers have proposed many FIR filters to meet above design specifications. In this paper, two different but efficient methods have been implemented in Xilinx software to improve the performance metrics in terms of speed, area and power. The target device is Spartan-3 Field   Programmable Gate Array.

     The first FIR filter is implemented using a variable precision two dimensional fine grain pipeline technique. This technique is developed to improve the performance of the existing two dimensional pipeline gating. The second type of FIR filter is based on the technique of a Data transition Power Diminution Technique (DPDT). In this technique, the effective dynamic data ranges are determined and the unused functional blocks are not activated based on the input data. Due to the unused functional blocks, the power consumption is reduced.