Power Saving and Delay Analysis of Adder Circuit using Adiabatic Logic

Abstract

In the implementation of all Integrated circuits (IC), the design parameter power consumption is considered as important parameter. It is considered as top design challenge among all the challenges in the international Integrated Circuit (IC) roadmap technology. The implementation of low power VLSI circuits has been emerged as they are very high in demand because of the rapid growth in technologies.

     In the IC chips the transistor count is increasing rapidly and proportionally, as the semiconductor technology entered into nanotechnology scale. The portable and smart electronic gadgets requires more energy efficiency and compact in size. But this improvement increases the clock speed to satisfy the above specifications. Hence, the dynamic power dissipation of the circuits increased. The portable electronic gadgets that are always require high speed clock.

Due to this high speed of the clock the dynamic power dissipation is increased in the VLSI circuits. In the conventional Complementary Metal Oxide Semiconductor (CMOS) techniques, the power dissipation is minimized by supply voltage reduction, reducing the activity of the transistor switches and by considering the less load capacitance. These techniques will be useful to reduce some part of the power dissipation only and still power dissipation is taken place. The further power dissipation can be reduced using adiabatic logic technique.

    This paper has presented all the gates (NAND, NOR etc.) implementation using adiabatic logic. The complex circuits such as, full adder  and a Carry Look ahead Adder (CLA) circuits are implemented using adiabatic 2PASCL topology and also implemented in conventional CMOS technology. All these implementations are done in 180nm technology using VLSI full-custom cadence tools. The results of the above circuits are compared in terms of delay and power consumption. The comparison states that, the adiabatic logic circuits consume less power with little bit penalty of delay.