SoC Implementation of Two Step Parallel ADC using Cadence Tools

Abstract

This paper presents the circuit of digital control logic for a 2 step parallel ADC. The goal behind in designing the control logic for parallel ADC (Analog to Digital Converter) circuits is used in many integrated circuits for detection of ionizing radiation. The converter employs a two step parallel technique employing a resistive DAC and is configured as a fully differential circuit. The results which are obtained from two step are further combined by using digital error correction algorithm to produce the final output. To design two step parallel ADC the following blocks are required i.e. comparator, resistive DAC, digital error correction block. All blocks are coded using Verilog HDL and compiled using Ncvlog Simulator, synthesized by using RTL Compiler and finally implemented on SoC Encounter.This paper presents the circuit of digital control logic for a 2 step parallel ADC. The goal behind in designing the control logic for parallel ADC (Analog to Digital Converter) circuits is used in many integrated circuits for detection of ionizing radiation. The converter employs a two step parallel technique employing a resistive DAC and is configured as a fully differential circuit. The results which are obtained from two step are further combined by using digital error correction algorithm to produce the final output. To design two step parallel ADC the following blocks are required i.e. comparator, resistive DAC, digital error correction block. All blocks are coded using Verilog HDL and compiled using Ncvlog Simulator, synthesized by using RTL Compiler and finally implemented on SoC Encounter.