Design And Implementation Of A Cyclic ADC For CMOS Image Sensors

Abstract

The constant strive for improvement of digital video capturing speeds together with power efficiency increase, has lead to tremendous research activities in the image sensor readout field during the past decade. The improvement of lithography and solid-state technologies provide the possibility of manufacturing higher resolution image sensors, as they provide possibilities for reduced power consumption and integration of complete on-chip cameras. With the increase of image sensors’ resolution and frame rate, traditional serial readout schemes become more laborious to design and in many cases simply unachievable for certain required readout speeds. This transfer however imposes additional demands to parallel ADC designs, mainly related to achievable accuracy, area and power. In this paper a 12-bit Cyclic ADC (CADC) is designed and implemented in 180nm CMOS technology aimed for column-parallel readout implementation in CMOS image sensors. The multiple CADC sub-component architectures and few various Multiplying DAC (MDAC) structures have been re-examined and implemented. Three comparator architectures have been explored and a dynamic interpolative Sub-ADC is presented. Finally, some weak spots degrading the performance of the carried-out design have been analyzed. As an architectural improvement possibility two MDAC capacitor mismatch error reduction techniques have been presented.