Optimization and Effective analysis of Full Adder Circuit Design in 45nm Technology

Abstract

In this paper work, a new XOR logic gate and multiplexer logic has been proposed. Proposed design shows acceptable output logic levels with noise margin of 0.5V with 1.0V as input signals in 45nm technology. A full adder design for single bit has been implemented using proposed XOR gate, pass transistor logic multiplexer. The full adder designed with 12 transistors shows power dissipation of 7.74nW and maximum output delay 59.74nS. This circuit works with well reduced supply and simulations have been carried out for 0.8V, 1.0V & 1.2V supply voltage in the step of 0.2V. Simulations are performed by using CADENCE based on gpdk45 library CMOS technology. Simulation result provides the advantage of the newly designed adder circuit against the conventional adder circuits. Consumption of power for proposed full adder has been compared with earlier reported full adder circuits, this proposed design circuit gives better performance in terms of power consumption, speed and transistor count.