ASIC Implementation of Lossless High Speed Serial Compression Using X-Match Process

Abstract

The paper presents a unique Very Large Scale Integrated Ciruit structural design for high-speed data compressor design which implements the X-Match process. The top level block diagram mainly consists of 5 units, namely, First in First out (FIFO), Match unit logic, CAM (content addressable memory) Comparator, X-match Unit, and Output-stage (DE-x-match) unit. The contentaddressable memory (CAM) unit produces a set of hit signals which identify those positions whose symbols in a specified window are the same as the input symbol. These hit signals are then passed to the X-match unit which determines both match length and location to form the kernel of compressed data. These two items are then passed to the output-stage unit for packetisation before being sent out. Logic density increases have made feasible the implementation of
multiprocessor systems which are able to meet the intensive data processing demands of highly concurrent systems. This design involves trade off that affects the compression performance, latency, and throughput. The design is implemented in ASIC. Ncvlog simulator is used for simulation, RTL Complier is used for Schematics and to get reports like area, power, timing, and SOC Encounter tool is used for Synthesis (Floor Plan, Partition, Routing, Pre CTS & Post CTS Synthesis, Clock Tree Synthesis) and finally the GDS II file – a complete chip fabrication is obtained.