Efficient Design Methodologies for Optimizing the Leakage Power in FPGAs

Abstract

The scaling of the CMOS technology has precipitated an exponential increase in both sub-threshold and gate leakage currents in modern VLSI designs. Consequently, the contribution of leakage power to the total chip power dissipation for CMOS designs is increasing rapidly, which is estimated to be 40% for the current technology generations. In FPGAs, the power dissipation problem is further aggravated when compared to ASIC designs because FPGA uses more transistors per logic function when compared to ASIC designs. Consequently, in the nanometer technology, the leakage power problem is pivotal to devising power-aware FPGAs. This paper focuses on the architectural techniques for leakage power reduction in FPGAs. In this paper the multi-threshold CMOS (MTCMOS) techniques are introduced to FPGAs to permanently turn OFF unused resources of the FPGA to reduce the power dissipation and the leakage power reduction technique in FPGAs on the use of input dependency is developed. This paper focuses on the reduction of leakage power with respect to CAD tools for the implementation of FPGAs.