Design and Verification of Impedance Matcher in a High Speed Serial IO Interface in 14-nm Technology

Abstract

A High Speed Interface corresponding to a PCIe (Peripheral Component Interconnect Express), DDR (Double Data Rate) or USB (Universal Serial Bus) suffices the need for speed, but it is important to eliminate the voltage reflections in the transmission line in the backplane and thus improve signals integrity. This is achieved by a Voltage-mode impedance Matching circuit, connected to the differential channel of the  High Speed Serial IO (Input-Output) Interface. A pair of Replica Circuits (shunt resistors) with switches are used for calibrating the impedance to be matched with that of the effective resistance obtained at the channel. This is controlled by a Finite State Machine that takes the decision of switching the resistors, which help to match the voltage potential at their respective ends. This decision is made baseed on the feedback received from a pair of comparators, which are prereferrenced with voltage levels, which are appropriate with equivalent voltages corresponding to the notion of effective resistance.