Design and Verification of High Speed IO Transmitter in 14nm Technology

K Nagaraju; K Rajagopal

K Nagaraju M.Tech Student, CVR College of Engineering/ECE Department, Hyderabad, India.
K Rajagopal Asst. Professor, CVR College of Engineering/ECE Department, Hyderabad, India.

Abstract

For many years, parallel I/O schemes ruled the chip to chip, board to board or backplane communication. Parallel I/O had to experience performance issues like crosstalk, signal integrity and increased skew after passing certain I/O clockfrequency rates [1]. Also parallel I/O methods increased the complexity of the hardware (high pin count, more wires) and made bandwidth sharing inevitable. In many new communication protocols serial data transmission has become very common due to low pin count (reduced cost). Serial I/O methods can also transmit at much higher clock rates per bit transmitted, thus outweighing the parallel transmission method. High speed serialization with large bandwidth plays a major role in transmitter of high speed interfacing circuits such as PCIe, USB, and SATA. Various encoding schemes are used based on the protocols. Efficient equalizers with interface units are required to avoid ISI (Inter Symbol Interference) and to drive the back-panel line. This also makes the design complex, which in turn makes the design verification and validation more challenging.