SoC Based Sigma Delta ADC Using ANFIS Algorithm for ECG Signal Processing Systems

Abstract

This paper presents a design of low power sigma delta ADC by using ANFIS algorithm which is applicable for high resolution ECG signal processing systems. The ECG signal analysis which is also known as a comprehensive analysis of the Heart, which helps for collecting the information of abnormal and normal conditions of the heart. The resolution of the ECG signal helps in the diagnosis of heart abnormalities. With the proposed design, the resolution of the ECG signal is improved and reduced power consumption levels of ADC.  The ANFIS algorithm is used to decide the sampling clocks of ADC which changes the power consumption levels in the ECG system. The main advantage of this ANFIS algorithm is to take instantaneous decisions. This ANFIS system can also be called as an intelligent system which makes use of neural networks. The ECG signal data is used as an input data for implementing the whole system SoC (System-on-chip) design using 90nm technology. The SoC includes the integration of 14 bit sigma delta ADC, ANFIS system, multiplexer, down sampling and up sampling circuits. The algorithm is designed in MATLAB and the whole system is modelled using VERILOG language. The simulation results were shown in Xilinx system generator, the synthesis is performed in Synopsys Design vision. The physical design of the chip is carried out in Cadence Encounter tool. The complete system can operate at 400 MHZ frequency and the power consumption of the system can be given as 15mw. This high resolution low power system level design is used for health care monitoring applications.