Design of Inexact Speculative Adder for High Performance Applications

Abstract

The low power and less area are equally vital in the implementation of high speed adders. The response time as the key point is also considered and focused for the optimization and considered for real-time interfaces. The general block schematic of the ISA consists of a carry speculation (SPEC) block, an addition block (ADD) and an error compensation (COMP) block. The Inexact Speculative Adder (ISA) design therefore, improves speed, reduces power consumption, propagation delay and accuracy management due to a short speculative path and to an error compensation technique. This technique allows to precisely controlling errors. The simulationand synthesis is carried out using CADENCE tools in 90nm CMOS technology. The power consumption and area occupied by the design is presented.