High-efficiency Low-power Flash ADC for High-speed Transceivers

Abstract

Modern communication systems require higher data rates which have increased the demand for the high speed transceivers. For a system to work efficiently, all blocks of that system should be fast.. This fact has led researchers to develop high speed analog to digital converters (ADCs) with low power consumption. Among all the ADCs, Flash ADC is the best choice for faster data conversion because of its parallel structure. This paper work describes the design of such a high speed and low power Flash ADC for the analog front end (AFE) of a transceiver. A high speed highly linear track and hold (T&H) circuit is needed in front of ADC which gives a stable signal at the input of ADC for accurate conversion. Averaging technique is employed in the preamplifier array of ADC to reduce the static offsets of preamplifiers. The averaging technique can be made more efficient by using the smaller number of amplifiers. This can be done by using the interpolation technique which reduces the number of amplifiers at the input of ADC. The Flash ADC is designed and implemented in 180 nm CMOS technology for the sampling rate of 1.6 G Samples/sec. The bootstrap T&H consumes power of 27.95 mW from a 1 V supply and achieves the signal to noise and distortion ratio (SNDR) of 37.38 dB for an input signal frequency of 195.3 MHz The ADC with ideal T&H and comparator consumes power of 78.2 mW and achieves 4.8 effective number of bits (ENOB).