High Performance Operational Amplifier for Pipelined Analog to Digital Converters

Abstract

As electronics and telecommunication worlds are moving fast towards digitalization and there is an ever increasing demand on speed and accuracy of the processed data, the need for high speed and high resolution ADCs has grown dramatically over recent years. Pipelined ADC is the architecture of choice in high speed and medium resolution applications. Op-Amps are basic building blocks of a wide range of analog and mixed signal systems. In this paper a Op-Amp is designed using 90nm CMOS technology, the small voltage difference can be around tens of millivolts is amplified by this Op-Amp. As new generations of CMOS technology tend to have shorter transistor channel length and scaled down supply voltage, the design of Op-Amps stays a challenge for designers.The main focus in this work is the Op-Amp design to meet the requirements needed for the 12-bit pipelined ADC. The Op-Amp provides enough closed-loop bandwidth to accommodate a high speed ADC (around 300MSPS) with very low gain error to match the accuracy of the 12-bit resolution ADC. The amplifier is placed in a pipelined ADC with 2.5 bit-per-stage (bps) architecture to check for its functionality. The Effective Number of Bits (ENOB) stays higher than 11 bit and the SNR is verified to be higher than 72 dB for sampling frequencies up to 320 MHz. Index Terms—ADC, Op-amp, CMOS, Low supply,bandwidth. Pipelined, Gain Boosting, CMFB, Flash,MDAC.