A Low Power, Leakage Reduction, High Speed 8-Bit Ripple Carry TSPC Adder using MTCMOS Dynamic Logic

Abstract

In Every IC design adder is basic building block to perform arithmetic operations. This paper presents new TSPC (True Single Phase Clock) adder for 8-bit operations using MTCMOS dynamic logic. The proposed design comprises of 18-transistors instead of 21-transistors used in existing design. The design also has advantage of power trade-off where it consumes only 384.5pW with reduced leakage power from 96 to 99% in sleep mode of circuit operation. MTCMOS Dynamic technology includes both HVT(High VTH) and LVT(Low VTH) Cells. HVT Cells are used as power switch and LVT Cells are used for actual logic operation to increase speed performance of the circuit. Conventional CMOS logic has more static power dissipation. In this paper MTCMOS dynamic logic is introduced to eliminate static power dissipation. The proposed design is implemented using 45 nm technology with supply voltage(VDD) of 1V.