Implementation of Memory Controller using Cadence Tools

Abstract

The Controller is designed which allows a high degree of programmability and interfaces many other memory devices which will be very flexible in nature to be programmed with other devices. To achieve throughput or latency multiple abstraction layers are present. The Controller provides the access of memory, executes in parallel form which leads to less logic utilization. This type of memory controllers are used in double data rate synchronous dynamic random access memory. The Memory Controller and Core Memory Controller are implemented using Cadence ASIC 45nm technology. Blocks are tested using ncvlog simulator, RTL schematics are generated using RTL Compiler and finally GDS-II file is obtained by using SoC Encounter. So the proposed Double data rate synchronous dynamic random access memory controller works with very less logic utilization, route and offset delay.