Design of Fast Locking ADPLL via FFC Technique using VHDL-AMS

Abstract

In this paper ADPLL is designed via feed forward compensation technique and implemented using VHDL mixed signal Modeling technique in CADENCE. The use of mixed signal is that it can simulate SPICE codes, VHDL codes, Verilog codes and Verilog –A codes at a time using both SPICE simulator and Incisive Unified Simulator. The ADPLL consists of PFD, P2D, FDLPF, MD, LC and DCO blocks.The PFD block was designed using transistors. The FDLPF, LC and DCO blocks were designed using VHDL. The MD and P2D blocks were designed both by using VHDL and transistors. The implemented ADPLL achieves a fast frequency locking via the proposed feed-forward compensation algorithm, reduces power consumption and wide tunable frequency range.The designed ADPLL is very much suitable for SOC applications.