Design of Sub-Threshold Source Coupled Logic Families for Low Power Applications

  • K.A. Jyotsna CVR College of Engineering/ECE Department, Hyderabad, India
  • P. Satish Kumar ACE Engineering College/ ECE Department, Hyderabad, India
  • B.K. Madhavi Sreedevi Engineering College/ ECE Department, Hyderabad, India

Abstract

In this paper Standard cell libraries of Sub threshold Source Coupled Logic (STSCL) are developed in 90nm and 45nm technology using cadence virtuoso at 1V power supply. These gates are further used to design digital
subsystems like Arithmetic logic unit (ALU) which work at low supply voltages and consume less power with promising performance.

Published
2016-06-30
Issue
Vol 10 (2016): CVR Journal of Science and Technology
Section
Articles
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