Low-Power Successive Approximation ADC with 0.5 V Supply for Medical Implantable Devices

Abstract

In this paper the design and implementation of very low-power Analog to Digital converter, which is used in medical implantable devices like pacemakers et al. The ADC uses a successive approximation architecture and operates with a low supply voltage is 0.5 V. A suitable dynamic twostage comparator is selected due to its energy efficiency and capability of working in low supply voltages. This ultra-low power 10-bit ADC is Implemented in a 90nm Complimentary Metal-Oxide semiconductor (CMOS) technology, this ADC consumes 12nW at supply voltage of 0.5V and sampling frequency of 1kS/s with figure of merit 0.14pJ/Conversion. It has a signal-to-noise-and-distortion (SINAD) ratio of 60.29dB and effective-number-of-bits (ENOB) of 9.72 bits.