An efficient sense amplifier design for STT-RAM in 45nm hybrid CMOS process

Abstract

In this paper different sense amplifier (SA) circuits for Spin Torque Transfer – Random Access Memory (STTRAM) have been designed. Their performance is evaluated in 45nm hybrid-CMOS process. The goal is to design an efficient sense amplifier with lower power consumption, better read cycle stability and to reduce the access time. Analysis and design have been done for two circuit’s i.e. conventional selfreference sensing (CSRS) scheme and non-destructive selfreference sensing (NDSR) scheme. The results show that CSRS provides good sense margin by trading power and performance. NDSR on the other hand improves the access
time, reduces power consumption but with a reduced sense margin.