Hazards and Glitch Power Reduction of CMOS Full Adder in 90nm Technology

Abstract

In This paper we discuss the glitch and hazard power compensation techniques which involves reducing the undesired switching of combinational circuits in order to save the dynamic power for CMOS stander cell designs in 90nm. In nanometer CMOS technologies the power consumption is become a serious concern. The total power consumption is mainly due to the dynamic and leakage power consumptions. In CMOS circuits a glitch occurs when differential delay at the inputs of a gate is greater than inertial delay, which gives an amount of power consumption. In lower technology nodes this glitch power is a major prominent. Experimental results gives 12% to 50% reduction in top 10 peak undesired transition. The proposed methodology has been validated using cadence 90nm gpdk technology libraries.