Technology Scaling And Low Power Design Techniques

  • T. Esther Rani CVR College of Engineering, Department of ECE., Ibrahimpatan, R.R.District, A.P., India.
  • Rameshwar Rao Hon‘ble VC, JNT University, Hyderabad, India.
  • M. Asha Rani JNT University, Department of ECE, Hyderabad, A.P., India.

Abstract

Scaling the feature size of transistor made a remarkable advancement in silicon industry. The demand for power-sensitive design has grown significantly in recent years due to growth in portable applications. The need for power-efficient design techniques is increasing. Various efficient design techniques have been proposed to reduce both dynamic as well as static power in state-of-the-art VLSI applications. In this paper, different circuit design techniques both static and dynamic are discussed that reduce the power consumption.

Published
2019-02-20