Design of an Op-Amp Based Low Voltage Low Dropout Regulator Using 180nm CMOS Technology

  • Silpa kesav CVR College of Engineering, Department of ECE, Ibrahimpatan, R.R.District, A.P., India
  • K.S. Nayanatara CVR College of Engineering, Department of ECE, Ibrahimpatan, R.R.District, A.P., India
  • B.K. Madhavi CVR College of Engineering, Department of ECE, Ibrahimpatan, R.R.District, A.P., India

Abstract

This paper describes the designing of a Low Voltage, Low Dropout (LVLD) Regulator with fast self-reacting (FSR) technique in 0.18 μm CMOS process. The LVLD Regulator provides 1.2 V regulated output voltage. The design procedure includes pass transistor, error amplifier, fast self-reacting path and bandgap reference (BGR) circuit. The pass transistor is designed for a desired minimum dropout voltage. The error amplifier has been developed with a gain of 65 dB and UGB of atleast 1 MHz. Curvature compensated CMOS BGR with 1.8 V supply has been developed to produce 0.8 V output voltage with better temperature coefficient.

Published
2019-02-18
Issue
Vol 3 (2012): CVR Journal of Science and Technology
Section
Articles
Copyright (c) 2012 Creative Commons Licence CVR Journal of Science & Technology by CVR College of Engineering is licensed under a Creative Commons Attribution 4.0 International License.