Design and Implementation of FIR Filter using Low Power and High-Speed Multiplier and Adders

Abstract

The Finite Impulse Response (FIR) filter is robust and high stable architecture rather than Infinite Impulse Response (IIR) Filter for the speech and image processing applications. In this paper, a high speed and low power FIR filter is designed and implemented using Radix-4 modified Booth Multiplier and Carry Look Ahead (CLA) adder. The Booth multiplier reduces the accumulation computation time in the multiplication of filter inputs and coefficients. CLA is used to reduce the critical path delay of the normal Ripple carry adder, which is used for the addition for the FIR filter. The 8-tap direct form FIR filter is implemented using Booth multiplier and CLA, and it is simulated and synthesized. The delay and power corresponding to these blocks are computed and presented. The utilization summary with respect to target FPGA of the each block is presented.