High Performance ALU Using Carry Look-ahead Adder

V Silpa kesav; G Sai Srinadh; Shaik Javeed

V Silpa kesav Asst. Professor, CVR College of Engineering/ECE Department, Hyderabad, India.
G Sai Srinadh M.Tech student, CVR College of Engineering /ECE Department, Hyderabad, India
Shaik Javeed M.Tech student, CVR College of Engineering /ECE Department, Hyderabad, India.

Abstract

A Low Power 8-bit Arithmetic Logic unit (ALU) using a Carry look-ahead adder (CLA) and placing Low Vt (LVt) cells in Critical path is anticipated. The ALU is designed in 90nm CMOS technology. ALU is the most essential circuit in any processor. It consists of AE, LE, CLA and CE. This ALU is designed to calculate Arithmetic and Logical operations. Power and Delay values of different 8-bit adders like CLA, Sparse and Ripple Carry Adder (RCA) are designed and compared. The simulation results show that the design of ALU using CLA and incorporating High Vt and Low Vt cells in the CLA gives more power and delay efficient than with only Standard threshold voltage cells.